1. Field of the Invention
The present invention relates to a semiconductor device and a wiring board.
2. Description of Related Art
FIG. 16 is a sectional view showing a configuration of a semiconductor device of a related art. A semiconductor device 100 has an interposer 202 and a single semiconductor chip 220. On the interposer 202, the semiconductor chip 220 is mounted with its circuit formation plane facing upward with a mount material 214. The semiconductor chip 220 is encapsulated with mold resin 224.
The interposer 202 includes an insulating layer 204 in which a plurality of wirings 212 are provided and solder resist 206 that covers its rear surface. Moreover, a power supply/ground layer 208 is provided in a layer in the inside of the insulating layer 204. An exposed part of the wiring 212 and a circuit (not illustrated) on the semiconductor chip 220 are electrically connected together by a wire 222.
FIG. 15 is a plan view of the power supply/ground layer 208. A sectional view taken along the line XVI-XVI of FIG. 15 corresponds to FIG. 16.
When letting an electric signal pass through the wiring 222, impedance matching needs to be achieved over the whole length of the wiring. If the impedance matching is not achieved, then reflection of the signal and waveform distortion will arise and a transmission characteristic will deteriorate. An influence of impedance mismatching is great especially when transmitting a high speed signal.
In the semiconductor device 100, the plurality of wirings 222 have fixed characteristic impedance with respect to the power supply/ground layer 208 in the inside of the wiring board 208 acting as an electric conductor reference plane, and the impedance matching is achieved over the whole length of the wiring.
Incidentally, as prior art documents relevant to the present invention, Patent Document 1 and Patent Document 2 can be enumerated.
Patent Document 1 is an example of a semiconductor device with a single semiconductor chip mounted thereon, which shows a configuration in which a power supply layer and a ground layer for formation of the characteristic impedance with a strip line structure are provided in the inside of a multilayer ceramic board.
Moreover, Patent Document 2 discloses a configuration that has an analog signal, a digital signal, an analog signal reference (electric conductor reference plane), and a digital signal reference in a board, in which an interval between the analog signal and the analog signal reference is set longer than an interval between the digital signal and the digital signal reference. Patent document 2 insists that this configuration enables desired characteristics of an analog signal and a digital signal to be altered, so that the characteristic impedance matching may be achieved.    [Patent Document 1] Japanese Patent Application Laid Open No. Hei 6 (1994)-244305    [Patent Document 2] Japanese Patent Application Laid Open No. 2006-86505